The present invention relates, in general, to the design and testing of integrated circuits, and, more specifically, to a method and system for use in the hierarchical design and testing of integrated circuits, a program product embodying the method and integrated circuits made in accordance with the method.
The complexity of semiconductor circuits often requires partitioning the circuit design into several modules or blocks, generally referred to as design hierarchy, blocks that can verified and layed out independently from each other. This approach has been used for a long time and has several benefits, the most significant of which are to accelerate the design by allowing several designers to work in parallel and to reduce the difficulty for the design automation tools by avoiding the need to manipulate the description of the entire circuit at once. However, test automation tools do not always offer an acceptable solution for handling design hierarchy. Many test automation tools still require processing the entire circuit at once. Other test automation tools do use hierarchical test methods. However, they require complete isolation of each module such that all inputs are controllable and all outputs are observable. In a paper entitled xe2x80x9cA structured and Scalable Mechanism for Test Access to Embedded Reusable Coresxe2x80x9d, ITC ""98. paper 12.1, Marinessen et al disclose a typical example of a hierarchical method imposing this restriction. Many similar methods have been proposed recently.
All of these methods suffer from the same drawbacks. They require a large number of additional logic gates, each module pin requires test-dedicated circuitry to provide the required isolation, the test-dedicated circuitry adversely impacts system timing because the functional signals must traverse the test-dedicated circuitry, the hierarchical design does not permit communication of signals between modules to be tested xe2x80x9cat-speedxe2x80x9d because the test-dedicated circuitry is usually connected to low-speed clocks and accessed through a standard Test Access Port (TAP), the most popular one being the IEEE 1149.1.
The present invention addresses these drawbacks with a novel method that minimizes the use of test-dedicated circuitry by using functional memory elements to provide module isolation, eliminates the impact on system timing by manipulating the scan control signals, provides at-speed testing of logic and/or interconnection wires between modules by using the system clock connected to the functional memory elements, and facilitates at-speed testing of modules with asynchronous clocks by reducing significantly the number of gates required to implement multiple controllers. The present invention also provides a novel integrated circuit constructed in accordance with the method. The best mode of implementing the method of the present invention is to automate the method using a suitable computer system.
One aspect of the present invention is defined as a method for use in the hierarchical design of integrated circuits having at least one module, each the module having functional memory elements and combinational logic, the method comprising reading in a description of the circuit; replacing the description of each functional memory element of the modules with a description of a scannable memory element configurable in scan mode and capture mode; partitioning each module into an internal partition and a peripheral partition by converting the description of selected scannable memory elements into a description of peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; modifying the description of modules in the circuit description so as to arrange the memory elements into scan chains in which peripheral and internal scannable memory elements of each module are controlled by an associated module test controller when configured in internal test mode; and peripheral scannable memory elements of each module are controlled by a top-level test controller when configured in an external test mode; and verifying the correct operation of the internal test mode and the external test mode of the circuit.
Another aspect of the present invention is defined as an integrated circuit having a plurality of modules, each the module having functional memory elements and combinational logic, the integrated circuit comprising each module being partitioned into an inner partition and a peripheral partition, the inner and peripheral partitions being delimited by peripheral memory elements, the peripheral memory elements being functional memory elements and being configurable in an internal test mode, an external test mode and a normal operating mode; each functional memory element and the peripheral memory element being configurable in shift mode for loading test stimuli thereinto and unloading test response data therefrom and in normal operating mode; the peripheral memory elements including: input peripheral memory elements one module input in the fanin of its data input; and output peripheral memory elements having at least one module output or an input peripheral memory element in the fanout of its data output; the peripheral memory elements being arranged in at least one scan chain; and control logic means associated with each the at least one scan chain responsive to control signals for configuring the peripheral memory elements in an internal test mode, an external test mode and a normal operating mode.
A further aspect of the present invention is defined as a system for use in the hierarchical design of integrated circuits having at least one module, each module having functional memory elements and combinational logic, the system comprising a general- or special-purpose digital computer; means for reading in a description of the circuit; means for replacing the description of each functional memory element of the modules with a description of a scannable memory element configurable in scan mode and capture mode; means for partitioning each module into an internal partition and a peripheral partition by converting the description of selected scannable memory elements into a description of peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; means for modifying the description of modules in the circuit description so as to arrange the memory elements into scan chains in which peripheral and internal scannable memory elements of each module are controlled by an associated module test controller when configured in internal test mode and peripheral scannable memory elements of each module are controlled by a top-level test controller when configured in an external test mode; and means for verifying the correct operation of the internal test mode and the external test mode of the circuit.
A further aspect of the present invention is defined as a program product for use in the hierarchical design of integrated circuits having at least one module, each the module having functional memory elements and combinational logic, the program product comprising a computer readable storage medium, means recorded on the medium for reading in a description of the circuit; means recorded on the medium for replacing the description of each functional memory element of the modules with a description of a scannable memory element configurable in scan mode and capture mode; means recorded on the medium for partitioning each module into an internal partition and a peripheral partition by converting the description of selected scannable memory elements into a description of peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; means recorded on the medium for modifying the description of modules in the circuit description so as to arrange the memory elements into scan chains in which peripheral and internal scannable memory elements of each module are controlled by an associated module test controller when configured in internal test mode; and peripheral scannable memory elements of each module are controlled by a top-level test controller when configured in an external test mode; and means recorded on the medium for verifying the correct operation of the internal test mode and the external test mode of the circuit.